Packaging of integrated circuits with carbon nano-tube arrays to enhance heat dissipation through a thermal interface

ABSTRACT

According to one aspect of the invention, a method of constructing an electronic assembly is provided. A layer of metal is formed on a backside of a semiconductor wafer having integrated formed thereon. Then, a porous layer is formed on the metal layer. A barrier layer of the porous layer at the bottom of the pores is thinned down. Then, a catalyst is deposited at the bottom of the pores. Carbon nanotubes are then grown in the pores. Another layer of metal is then formed over the porous layer and the carbon nanotubes. The semiconductor wafer is then separated into microelectronic dies. The dies are bonded to a semiconductor substrate, a heat spreader is placed on top of the die, and a semiconductor package resulting from such assembly is sealed. A thermal interface is formed on the top of the heat spreader. Then a heat sink is placed on top of the thermal interface.

BACKGROUND OF THE INVENTION

[0001] 1). Field of the Invention

[0002] This invention relates to a method of constructing an electronicassembly and to an electronic assembly which may be made according tothe method of the invention.

[0003] 2). Discussion of Related Art

[0004] Integrated circuits are formed on semiconductor wafers. Thewafers are then sawed into semiconductor chips also known asmicroelectronic dies. Each semiconductor chip is then mounted to apackage substrate. An integrated circuit within the semiconductor chipcan be powered up and data signals can be sent to and received from theintegrated circuit via the package substrate.

[0005] When the integrated circuit is powered up, heat is generated onthe semiconductor chip which could cause destruction of the integratedcircuit if the heat is not transferred away. A thermally conductiveplate, such as a heat spreader or a heat sink, is often located next tothe semiconductor chip. A thermally conductive grease may be locatedbetween the semiconductor chip and the thermally conductive plate. Thethermally conductive grease contacts the semiconductor chip and thethermally conductive plate on opposing sides and acts as a thermalinterface between the semidonductor chip and the thermally conductiveplate. Heat can then be transferred from the semiconductor chip throughthe grease to the thermally conductive plate, from where heat can betransferred to a heat sink or other device and can be convected into theambient.

[0006] The use of grease as a thermal couple is often unsuitable forhigh power applications. A thermally conductive grease has a relativelylow thermal conductivity and thus provides a substantial thermal barrierfor heat transferring from the die to the thermally conductive plate. Asa result, an insufficient amount of heat is transferred to the heatspreader or heat sink when a large amount of heat is generated on thesemiconductor chip.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The invention is described by way of examples with reference tothe accompanying drawings, wherein:

[0008]FIG. 1 is a top plan view of a semiconductor wafer including aplurality of integrated circuits formed thereon;

[0009]FIG. 2 is a cross-sectional side view of an integrated circuitformed on the wafer;

[0010]FIG. 3 is a cross-sectional side view of the integrated circuitwith a layer of aluminum having been deposited;

[0011]FIG. 4 is a cross-sectional side view of the integrated circuitwith a porous layer of aluminum oxide formed on the layer of aluminum;

[0012]FIG. 5 is a cross-sectional side view of the integrated circuitwith nickel catalysts deposited into the pores;

[0013]FIG. 6 is a cross-sectional side view of the integrated circuitwith carbon nanotubes deposited into the pores of the aluminum oxidelayer;

[0014]FIG. 7 is a perspective view of a carbon nanotube;

[0015]FIG. 8 is a cross-sectional side view of the integrated circuitflipped over and with a layer of indium formed on the layer of aluminumoxide;

[0016]FIG. 9 is a top plan view of a portion of the semiconductor waferwith the integrated circuits separated into microelectronic dies;

[0017]FIG. 10 is a cross-sectional side view of a microelectronic diebonded to a semiconductor substrate;

[0018]FIG. 11 is a cross-sectional side view of the microelectronic diewith a heat spreader bonded to the indium layer;

[0019]FIG. 12 is a cross-sectional side view of a semiconductor packageincluding the microelectronic die, the semiconductor substrate, and theheat spreader; and

[0020]FIG. 13 is a cross-sectional side view of an electronic assemblyincluding the semiconductor package and a heat sink.

DETAILED DESCRIPTION OF THE INVENTION

[0021]FIG. 1 to FIG. 11 of the accompanying drawings illustrate a methodof constructing an electronic assembly. A layer of metal is formed on abackside of a semiconductor wafer having integrated formed thereon.Then, a porous layer is formed on the metal layer. A barrier layer ofthe porous layer at the bottom of the pores is thinned down. Then, acatalyst is deposited at the bottom of the pores. Carbon nanotubes arethen grown in the pores. Another layer of metal is then formed over theporous layer and the carbon nanotubes. The semiconductor wafer is thenseparated into microelectronic dies. The dies are bonded to asemiconductor substrate, a heat spreader is placed on top of the die,and a semiconductor package resulting from such assembly is sealed. Athermal interface is formed on the top of the heat spreader. Then a heatsink is placed on top of the thermal interface.

[0022]FIG. 1 illustrates a typical silicon semiconductor wafer 20 onwhich a plurality of integrated circuits 22 have been formed. FIG. 2illustrates a portion of the wafer 20 including one of the integratedcircuits 22.

[0023] The wafer 20 is circular in shape with an outer edge 24 with anindicator 26. The wafer has a diameter 28 of, for example, of 200 mm.The indicator 26 is a notch on the outer edge 24 of the wafer 20. Thewafer 20 includes a plurality of integrated circuits 22 arranged in anarray of rows and columns.

[0024] The integrated circuits 22 are square with sides 30 of, forexample, between 12 and 20 mm. The integrated circuits 22 includetransistors 32, alternating metal and dielectric layers 34, and contacts36. The contacts 36 have been attached to the wafer 20 on an adjacentside to the integrated circuit 22. The contacts 36 stand proud of asurface of the wafer 20.

[0025] As illustrated in FIG. 3, an aluminum layer 38 is then depositedby chemical vapor deposition onto a side of the wafer 20 opposing theintegrated circuit 22. The aluminum layer 38 is on a side of theintegrated circuit 22 opposing the contacts 36.

[0026] As illustrated in FIG. 4, a porous aluminum oxide layer 40 isthen formed on the aluminum layer 38. The porous aluminum oxide can beformed by anodic oxidation of the aluminum layer 38 in acids such assulfuric acid, phosphoric acid, and oxalic acid in the concentrationrange of 1-10% at 10-60 V. The aluminum oxide layer 40 includes aplurality of pores 42. A barrier layer of aluminum oxide has beenthinned down from ends 44 of the pores 42 adjacent to the aluminum layer38.

[0027] As illustrated in FIG. 5, nickel catalysts 46 are thenselectively deposited in the pores 42 of the aluminum oxide layer 40 bycathodic deposition. The cathodic deposition can be performed by usingalternating voltage. The nickel is deposited from a solution containingnickel sulfate at 10-50 g/l, boric acid at 10-50 g/l, and sulfuric acidat 2-4 g/l with a pH between 3 and 5 and a cathodic voltage between 10and 20 V. The nickel catalysts 46 are positioned at the ends 44 of thepores 42.

[0028] As illustrated in FIG. 6, carbon nanotubes 48 are then grown onthe catalysts 46 inside the pores 42 by selective plasma enhancedchemical vapor deposition and completely fill the pores 42.

[0029]FIG. 7 illustrates one of the carbon nanotubes 48. The carbonnanotubes 48 are cylindrical in shape with a height 50 of 5 microns, adiameter 52 of 500 angstroms, and a primary axis 54. The heights aretypically between 1 and 10 microns, and the diameters are typicallybetween 10 and 1000 angstroms. The carbon nanotubes 48 are single-walledbut may be multi-walled. The carbon nanotubes 48 are grown in the pores42 such that the primary axis 54 is perpendicular to the sides of theintegrated circuit 22. This is achieved by applying an electric fieldwhile growing the carbon nanotubes 48.

[0030]FIG. 8 illustrates the integrated circuit 22 after the integratedcircuit 22 has been flipped over and an indium layer 56 has been addedonto the aluminum oxide 40 layer by chemical vapor deposition.

[0031] As illustrated in FIG. 9, the semiconductor wafer 20 is then cutbetween the integrated circuits 22 to form individual singulatedmicroelectronic dies 58.

[0032]FIG. 10 illustrates one of the microelectronic dies 58 after beingseparated from the wafer 20. The microelectronic die 58 has been placedon top of a silicon semiconductor substrate 60. The contacts 36 havebeen heated to reflow and have bonded to the substrate 60.

[0033] As illustrated in FIG. 11, a heat spreader 62 is then positionedon top of the microelectronic die 58. The heat spreader 62 is athermally conductive member that has a width 64 of 70 mm. Walls 66extend downward from the heat spreader 62 but do not extend completelyto the substrate 60.

[0034] As illustrated in FIG. 12, the microelectronic die 58 thencompletely enclosed within a semiconductor package 68. Heat is appliedto the package 68 including the substrate 60, the microelectronic die58, and the heat spreader 62. Pressure is applied to opposing sides ofthe substrate 60 and the heat spreader 62. Due to the heat, the aluminumoxide layer 40 and the indium layer 56 have become flexible and thecombined thickness of the aluminum oxide layer 40 and the indium layer42 has decreased slightly. The carbon nanotubes 48 are now embedded inthe indium layer 56. Furthermore, the walls 66 of the heat spreader 62have now moved into contact with the substrate 60 to seal thesemiconductor package 68. The carbon nanotubes 48 can also bemechanically connected to the heat spreader 62.

[0035] As illustrated in FIG. 13, after the package 68 has been sealed athermal interface 70 is added to the top of the heat spreader 62. A heatsink 72 is then placed on top of the package 68 to form a completeelectronic assembly 74. The heat sink 72 is a thermally conductivemember having a base portion 76 and heat sink fins 78. The heat sink 72has a rectangular cross-section a width 80 of 140 mm.

[0036] In use, power is supplied to the integrated circuit 22. Thetransistors 32 begin to heat up as current conducts through a substratethat remains of the original wafer (see reference numeral 20 in FIG. 1),the aluminum layer 38, the aluminum oxide layer 40, and the carbonnanotubes 48. Due to the chemical bond between the aluminum and thecarbon nanotubes 48, the heat experiences very little thermal resistanceas the heat conducts between the aluminum and the carbon nanotubes 48.The carbon nanotubes 48 have an extremely high thermal conductivity andthermally couple the integrated circuit 22 to the heat spreader 62through the aluminum and the indium layer 56. The thermal resistance isespecially low in a direction of the primary axis 54 of the carbonnanotubes 48. The thermal resistance of the electronic assembly 74 iseven further reduced if at least 5%, preferably 15% or more, of thealuminum oxide layer 40 is covered with the carbon nanotubes 48. Thethermal resistance of the electronic assembly 74 is particularly low ifthe primary axes 54 of at least 20% of the carbon nanotubes 48 areparallel to each other. The combination of the chemical bond, thermalconductivity of the carbon nanotubes 48, and the orientation of thecarbon nanotubes 48 provides the system a very high thermalconductivity. As a result, the heat efficiently conducts from theintegrated circuit 22 to the indium layer 56.

[0037] Once through the indium layer 56, the heat is conducted to theheat spreader 62 where, due to the width 64 of the heat spreader 62, itquickly dissipates and conducts to the thermal interface 70. Afterconducting through the thermal interface 70, the heat conducts to theheat sink 72, another thermally conductive member with an increasedwidth 80. The heat conducts through the base portion 76 of the heat sink72 to the heat sink fins 78. Due to increased surface area created bythe fins 78, the heat efficiently convects to the surrounding air.

[0038] One advantage is that a thermal interface with a higher thermalconductivity is provided, especially when compared with thermal greasesand metallic layers. Another advantage is that the thermal interface hasa high mechanical strength. A further advantage is that a chemical bondis provided between the carbon nanotubes and the integrated circuitwhich promotes transfer of heat. A further advantage is that an improvedcontact between the integrated circuit and the thermal materials isprovided. A further advantage is that a thinner and more uniform thermalinterface is provided.

[0039] Other embodiments of the invention may use different methods ofdepositing the catalysts such as electroplating or electoless plating,and different catalysts such as cobalt, iron, rhodium platinum, nickelyttrium, or any combination thereof can be used as well. Alternativetechniques can be used to grow the carbon nanotubes including discharge,between carbon electrodes, laser vaporization of carbon, thermaldecomposition of hydrocarbons such as acetylene, methane, ethane, andgas phase chemical vapor deposition (CVD) which uses carbon monoxide andmetal carbonyls. More than one carbon nanotubes, either single ormulti-walled, may be grown in individual pores. The backsidemetallization of the wafer can also be accomplished by plasma vapordeposition (PVD) or plating, and other metals such as copper, aluminum,nickel, cobalt, gold, germanium, gallium, rubidium, rhodium, platinum,tin, bismuth, tin lead, palladium, or combinations thereof can be used.The heat sink can also be positioned directly on the indium layer andthe carbon nanotubes, and the heat spreader need not be used at all.

[0040] While certain exemplary embodiments have been described and shownin the accompanying drawings, it is to be understood that suchembodiments are merely illustrative and not restrictive of the currentinvention, and that this invention is not restricted to the specificconstructions and arrangements shown and described since modificationsmay occur to those ordinarily skilled in the art.

What is claimed:
 1. A method of forming an electronic assembly,comprising: growing a plurality of carbon nanotubes from amicroelectronic die having an integrated circuit formed therein; andpositioning the microelectronic die and a thermally conductive memberrelative to one another so that the carbon nanotubes are in a positionto thermally couple the integrated circuit to the thermally conductivemember.
 2. The method of claim 1, wherein the plurality of carbonnanotubes are grown on a side of the microelectronic die opposing theintegrated circuit.
 3. The method of claim 1, further comprising forminga layer of material on the side of the microelectronic die opposing theintegrated circuit.
 4. The method of claim 3, further comprising forminga porous layer of the material on the layer of material, the porouslayer having a plurality of pores in which the plurality of carbonnanotubes are grown.
 5. The method of claim 4, wherein the carbonnanotubes are cylindrical and each has a diameter between 10 and 1000angstroms and a height between 1 and 10 microns.
 6. The method of claim5, wherein the material is aluminum.
 7. The method of claim 6, whereinthe porous material is aluminum oxide.
 8. The method of claim 7, whereinthe pores have a barrier layer of aluminum oxide at an end adjacent tothe layer of aluminum.
 9. The method of claim 8, further comprisingthinning the barrier layer of aluminum oxide.
 10. The method of claim 9,further comprising depositing a catalyst into the pores.
 11. The methodof claim 10, wherein the catalyst is nickel.
 12. The method of claim 11,wherein the carbon nanotubes are grown on the catalyst.
 13. The methodof claim 12, further comprising forming a layer of a second material ona side of the porous layer opposing the barrier layer.
 14. The method ofclaim 13, wherein the second material is indium.
 15. A method forforming an electronic assembly, comprising: growing a plurality ofcarbon nanotubes from a microelectronic die having an integrated circuitformed therein.
 16. The method of claim 15, wherein the plurality ofcarbon nanotubes are grown on a side of the microelectronic die opposingthe integrated circuit.
 17. The method of claim 16, further comprisingforming a layer of a porous material on the side of the microelectronicdie opposing the integrated circuit, the porous material having aplurality of pores in which the carbon nanotubes are grown.
 18. Amethod, comprising: growing carbon nanotubes from a substrate; andthermally coupling an integrated circuit through the carbon nanotubeswith a thermally conductive member, whereafter the carbon nanotubes arestill attached to the substrate.
 19. The method of claim 18, furthercomprising transferring heat from the integrated circuit through thesubstrate and the carbon nanotubes to the thermally conductive member.20. The method of claim 19, further comprising convecting heat from thethermally conductive member.
 21. The method of claim 20, wherein thesubstrate and the thermally conductive member are different components.22. A method of constructing an electronic assembly from a firstcomponent including a microelectronic die having an integrated circuitand a second component including a thermally conductive member,comprising: growing carbon nanotubes from one of the components; andpositioning the first component and the second component so that thefirst component and the second component are thermally coupled to oneanother through the carbon nanotubes.
 23. The method of claim 22,wherein the carbon nanotubes are grown from a side of themicroelectronic die opposing the integrated circuit.
 24. The method ofclaim 23, wherein the carbon nanotubes are grown in pores of a porouslayer of material on the side of the microelectronic die opposing theintegrated circuit.
 25. A method for forming an electronic assembly,comprising: forming a plurality of integrated circuits on a wafer;forming a layer of aluminum on a side of the wafer opposing theintegrated circuits; forming a layer of porous aluminum oxide on thelayer of aluminum, the layer of porous aluminum oxide having a side anda plurality of pores, the pores having a barrier layer of aluminum oxideat an end adjacent to the layer of aluminum, the pores covering at least5% of a surface area of the side; thinning the barrier layer of aluminumoxide at the end of the pores; depositing nickel catalysts into thepores; growing carbon nanotubes in the pores, the carbon nanotubeshaving a cylindrical shape with diameters between 10 and 1000 angstromsand heights between 1 and 10 microns; forming a layer of indium on aside of the layer of aluminum oxide opposing the layer of aluminum; andseparating the wafer into microelectronic dies.
 26. The method forforming an electronic assembly of claim 25, further comprising bondingthe microelectronic dies with substrates.
 27. The method for forming anelectronic assembly of claim 26, further comprising bonding themicroelectronic die to a heat spreader which is larger than themicroelectronic die.
 28. An electronic assembly, comprising: amicroelectronic die having a die substrate and an integrated circuit onthe die substrate; a thermally conductive substrate; and a plurality ofcarbon nanotubes thermally coupling the microelectronic die to thethermally conductive substrate, each of the carbon nanotubes having oneend chemically bonded to one of the substrates.
 29. The electronicassembly of claim 28, wherein the carbon nanotubes are positionedbetween the thermally conductive substrate and a side of the diesubstrate opposing the integrated circuit.
 30. The electronic assemblyof claim 29, wherein the thermally conductive member is a heat spreaderwhich is larger than the microelectronic die.
 31. An electronicassembly, comprising: a microelectronic die comprising a substrate andan integrated circuit, the substrate having a side; a plurality ofcarbon nanotubes having first portions, second portions, and primaryaxes, the first portions being thermally coupled to the side of thesubstrate, at least 20% of the primary axes being substantially parallelwith one another; and a thermally conductive member thermally coupled tothe second portions of the carbon nanotubes.
 32. The electronic assemblyof claim 31, wherein the carbon nanotubes cover at least 5% of a portionof the side of the substrate with an area of at least 1 cm².
 33. Theelectronic assembly of claim 32, wherein at least 20% of the primaryaxes are substantially perpendicular to the side of the substrate 34.The electronic assembly of claim 33, wherein the carbon nanotubes aregrown on the side of the substrate opposing the integrated circuit.